1. At Hampoo, we are capable to produce the hard gold plating required for both contacts and gold fingers.

    The process begins after the copper etch with the PCBs tape laminated to leave only the desired area exposed. A nickel underlayer is electro-plated onto the PCB with a minimum thickness of 50 micro-inch. Nickel not only provides mechanical support, it also provides a diffusion barrier as well as an inhibitor to pore and creep corrosion. The 24 carat hard gold, immersed in a salt medium, is then electro-plated directly onto the nickel surface.

    Quality control for hard gold finishes includes thickness and tape adhesion tests. As you may expect, the price of gold requires solid process controls as the cost for errors would make even Auric shudder.

    A few design rules are required for gold fingers

    • No plated through holes are allowed in the plated area
    • No solder mask or silk screening can be present in the plated area
    • For panelization, always place gold fingers facing outward from the panel center
    • Connect all gold fingers with a 0.008” conductor trace at the edge to allow for manufacturing
    • Features can be placed on one or both sides to a depth of 25mm from the outside edge

    Having the capability to provide 24 carat hard gold PCB electroplating in-house not only ensures us to control over the process, it also allows us to significantly shorten the manufacturing lead time of quick turn PCBs when compared to subcontracting or outsourcing. 


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  2. In the high frequency domain, a signal or EM wave must propagate along the transmission path with uniform characteristic impedance. Whenever an impedance mismatch or discontinuity is encountered, a portion of the signal is reflected back to the transmitting end while remaining portion of the EM wave continues to travel to the receiving end. The severity of the signal reflection and attenuation depend on the magnitude of impedance discontinuity. When the magnitude of mismatched impedance increases, a larger portion of the signal is reflected and more attenuation or degradation of signal is observed at the receiver.
    The phenomenon of mismatched impedance is encountered at SMT pads of AC coupling (a.k.a DC blocking) capacitors, board to board connectors, and cable to board connector (e.g., SMA).
    In the case of SMT pad of AC coupling capacitor, as shown in Figure 1, a signal that travels along the PCB traces with 100 ohm differential impedance and 5 mils copper width, experiences an impedance discontinuity once it reaches the SMT pad with a wider copper (e.g., 30 mils width for 0603 package). This phenomenon is explained in Equation (2) and (1). The rise of copper’s cross sectional area or width increases the strip capacitance, which in turn causes capacitive discontinuity (i.e., negative surge) to the characteristic impedance of the transmission channel.
    In order to minimize the capacitive discontinuity, the reference plane area right under the SMT pads is cut out, and copper fill is constructed on the inner layer, as illustrated in Figure 2 and 3 respectively. This increases the distance between SMT pad and its reference or return path, which reduces the capacitive discontinuity. Micro stitching vias shall be inserted to provide electrical and physical connectivity between the original reference plane and the new reference copper on inner layer to have a proper signal return path to avoid EMI radiation issue.
    However, the distance “d” shall not be increased too much until strip inductance overrides strip capacitance and causes inductive discontinuity, as explained in Equation (3).


    Figure 1. Side view of PCB without plane cut-out



    Figure 2. Side view of PCB with plane cut-out


    Figure 3. Top view of PCB with plane cut-out

          
    C = strip capacitance (in pF)
    L = strip inductance (in nH)
    Zo = characteristic impedance (in ohm)
    ε = dielectric permittivity
    w = width of SMT pad
    l = length of SMT pad
    d = distance between SMT pad and reference plane underneath
    t = thickness of SMT pad

    The same concept is applicable to SMT pads of board to board (B2B) and cable to board (C2B) connectors, as shown in Figure 4 and 5 respectively.

    Figure 4. B2B connector
    Figure 5. C2B connector

    The proof of concept with analysis of TDR and insertion loss is presented in the subsequent section of this paper. The analysis is conducted by 3D modeling of SMT pad in EMPro software and subsequently being imported to Keysight ADS for simulation of TDR and insertion loss.

    Analyzing Effect of SMT Pad of AC Coupling Capacitor
    A 3D model of SMT with medium loss substrate is constructed in EMPro, where a pair of microstrip differential traces of 2 inches long and 5 mils wide in single ended mode, and 3.5 mils away from its reference plane enter the SMT pad of 30 mils wide at one end and exit it at another end. The copper area right under the SMT pads is cut out, the 3D model is shown in Figure 6.

    Figure 6. 3D model of SMT pad with cut-out on reference plane underneath

    The simulated plots of TDR and insertion loss are shown in Figure 7 and 8 respectively. SMT design without cut-out on reference plane causes impedance mismatch of 12Ω and insertion loss of -6.5dB at 20 GHz. Once cut-out is introduced to the reference plane area beneath the SMT pads, where “d” is set as 10 mils, the mismatched impedance improves to 2Ω and insertion loss of -3dB at 20GHz. Further increase of “d” causes strip inductance to override capacitance, results inductive discontinuity and in turn worsens the insertion loss (i.e., -4.5dB).

    Figure 7. Plot of simulated TDR

    Figure 8. Plot of simulated insertion loss

    Analyzing Effect of SMT Pad of B2B Connector
    A 3D model of SMT pad of B2B connector with pin pitch of 20 mils and pin width of 6mils, connected to a pair of microstrip differential traces of 5 inches long and 5 mils wide in single ended mode, and 3.5 mils away from its reference plane is constructed in EMPro. The thickness of SMT pad becomes 40 mils, inclusive of connector pin and solder, which is almost 40 times the thickness of the microstrip PCB trace.
    The capacitive discontinuity and higher signal attenuation are experienced when the copper thickness is increased. The phenomenon is shown in simulated plot of TDR and insertion loss in Figure 9 and 10 respectively. By cutting out the copper area right under the SMT pads with moderate “d” (i.e., 7 mils), impedance mismatch is minimized.

    Figure 9. Plot of simulated TDR

    Figure 10. Plot of simulated insertion loss
    Conclusion
    The analysis in this paper proves that insertion of a cut-out on the reference plane underneath the SMT pads reduces the impedance mismatch and increases the bandwidth of the transmission line. The distance between the SMT pad and its reference copper on an inner layer depends on the width of the SMT pad, and also the effective thickness of SMT pad inclusive of connector pin and solder. 3D modeling and simulation should be performed prior to PCB fabrication to ensure construction of a transmission channel with good signal integrity.

    References
    [1]  Eric Bogatin, “Signal Integrity-Simplified”, Prentice Hall, 2003
    [2]  Wave Reflection at an Impedance Discontinuity (includes animations)
    [5]  RF SMA, Samtec
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